MCBSTM32EXL【PDF 178/995 页】BOARD EVALUATION FOR STM32F103ZE

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Interrupts and events

RM0008

9.3

9.3.1

EXTI registers

Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions.

Interrupt mask register (EXTI_IMR)

Address offset: 0x00

Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

MR19

MR18

MR17

MR16

Reserved

rw

rw

rw

rw

15

MR15

rw

14

MR14

rw

13

MR13

rw

12

MR12

rw

11

MR11

rw

10

MR10

rw

9

MR9

rw

8

MR8

rw

7

MR7

rw

6

MR6

rw

5

MR5

rw

4

MR4

rw

3

MR3

rw

2

MR2

rw

1

MR1

rw

0

MR0

rw

Bits 31:20 Reserved, must be kept at reset value (0).

Bits 19:0 MRx: Interrupt Mask on line x

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is not masked

Note: Bit 19 is used in connectivity line devices only and is reserved otherwise.

9.3.2

Event mask register (EXTI_EMR)

Address offset: 0x04

Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

MR19

MR18

MR17

MR16

Reserved

rw

rw

rw

rw

15

MR15

rw

14

MR14

rw

13

MR13

rw

12

MR12

rw

11

MR11

rw

10

MR10

rw

9

MR9

rw

8

MR8

rw

7

MR7

rw

6

MR6

rw

5

MR5

rw

4

MR4

rw

3

MR3

rw

2

MR2

rw

1

MR1

rw

0

MR0

rw

Bits 31:20 Reserved, must be kept at reset value (0).

Bits 19:0 MRx: Event Mask on line x

0: Event request from Line x is masked

1: Event request from Line x is not masked

Note: Bit 19 is used in connectivity line devices only and is reserved otherwise.

178/995

Doc ID 13902 Rev 9

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